Fix wrong bits referred to in sctrctl.

riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

https://jira.riscv.org/browse/RVG-62

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Fix wrong bits referred to in sctrctl. #23

Closed rajnesh-kanwal closed 4 months ago

rajnesh-kanwal commented 4 months ago

M enable and MTE have moved to bits 2 and 9. Fix this in sctrctl csr section.

Reported-by: John Hauser