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riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
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Hello, I want to ask if has a kernel/qemu patch for ctr currently?Thank you. #27

Closed catrowlee closed 4 months ago

rajnesh-kanwal commented 5 months ago

Hi @solarises,

I am currently cleaning up patches. I will try to get those out in upstream mailing-list by end of this week.

rajnesh-kanwal commented 4 months ago

@solarises Please refer to https://github.com/riscv/riscv-control-transfer-records/issues/26.

catrowlee commented 4 months ago

Hi @solarises,

I am currently cleaning up patches. I will try to get those out in upstream mailing-list by end of this week.

thank you.

catrowlee commented 4 months ago

@solarises Please refer to #26.

thank you .