This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
Smctr depends on the Smcsrind extension, while Ssctr depends on the Sscsrind extension. Further, both Smctr and Ssctr depend upon implementation of S-mode.
Chapter 1 states (bold added):
The bold text should be removed.