riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
14 stars 4 forks source link

remove references to Smcsrind, upon which S*ctr no longer depends #29

Closed bcstrongx closed 1 month ago

rajnesh-kanwal commented 1 month ago

There is one more reference in intro.adoc.

bcstrongx commented 1 month ago

Thanks, I had forgotten to add intro.adoc to the commit. Fixed.

On Fri, Jun 7, 2024 at 3:27 AM Rajnesh Kanwal @.***> wrote:

There is one more reference in intro.adoc.

— Reply to this email directly, view it on GitHub https://github.com/riscv/riscv-control-transfer-records/pull/29#issuecomment-2154553330, or unsubscribe https://github.com/notifications/unsubscribe-auth/AXFCKAE6OC6P4M2G5I6EHA3ZGGDKPAVCNFSM6AAAAABI5IUCSSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDCNJUGU2TGMZTGA . You are receiving this because you were assigned.Message ID: @.***>