This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
Observe that the entry 0 is not as well documented and a small pseudo code that shows when recording the record is written to where wrptr is and wrptr is incremented and when popping wrptr is decremented and marked invalid would be useful clarifying addition
The siselect index range 0x200 through 0x2FF is reserved for CTR entries 0 through 255. This may want to be updated to state "logical entries 0 through 255"
The siselect index range 0x200 through 0x2FF is reserved for CTR entries 0 through 255.
This may want to be updated to state "logical entries 0 through 255"