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riscv / riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
Creative Commons Attribution 4.0 International
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3 feedback for v013 #4

Closed bcstrongx closed 1 year ago

bcstrongx commented 1 year ago

address issue #3