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riscv-control-transfer-records
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
https://jira.riscv.org/browse/RVG-62
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Earl Killian feedback
#6
Closed
bcstrongx
closed
7 months ago
bcstrongx
commented
8 months ago
Via email:
Spell out RAS as Return Address Stack the first time it is used per section, to avoid confusion with the other RAS
Define the CC encoding scheme (already have the decoding scheme)
Introduce configurable depth (including motivation) and what metadata is available in introduction
Via email: