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riscv / riscv-crypto

RISC-V cryptography extensions standardisation work.
https://wiki.riscv.org/x/MVcF
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Illegal condition for VWSLL operation #381

Open Mingku-Chang opened 6 months ago

Mingku-Chang commented 6 months ago

I guess that the VWSLL operation with (SEW == 64) is not allowed. Vector Crypto follows a lot of regulations from Vector. Therefore, results can't exceed 64-bit width. I recommend adding some statements to show readers that Vector has such a regulation.

nibrunieAtSi5 commented 6 months ago

You are right vwsll with SEW=64-bit (vsew=3) would mean an effective element width of 128-bit (EEW=2*SEW) which is not currently supported so this behaviour is reserved.

Note that they are other possible restrictions, for example if ELEN=32 then SEW=32-bit is also reserved (Since Zvbb could be supported alongside Zve32x for example). In that case I am not sure a specific mention of SEW==64 really make sense since it is not the only possible limitation. We could (should ?) mention that this instructions inherits element width constraint from RVV.

nibrunieAtSi5 commented 5 months ago

@kdockser for your consideration

wmat commented 4 months ago

Is this recommendation still valid? If yes, please transfer issue to riscv-isa-manual repo or let me know to do it. Thanks.