pull proposal for issue #221

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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pull proposal for issue #221 #270

Closed dansmathers closed 9 months ago

dansmathers commented 2 years ago

add mirrored view of clicintie/clicintip so software can quickly modify multiple interrupt enables for issue #221

Signed-off-by: Dan Smathers dan.smathers@seagate.com

tovine commented 2 years ago

I guess this also works with 64 bit accesses even though only 32 bit registers are specified (maybe there should be a note about this to remove ambiguity)?

I like the idea, not 100% sold on the name but I don't have a better alternative at the moment :)

dansmathers commented 2 years ago

I was trying to match wording with AIA since it seems similar. from aia spec: "Registers eip0 through eip63 contain the pending bits for all implemented interrupt identities, and are collectively called the eip array. Registers eie0 through eie63 contain the enable bits for the same interrupt identities, and are collectively called the eie array."