riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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CSR allocation (and tentative address): `mclicbase` #282

Closed a4lg closed 1 year ago

a4lg commented 1 year ago

Current documentation states that mclicbase CSR would have an address of 0x3?? but 0x3?? indicates machine-mode read-write CSRs. It seems inappropriate for a read-only CSR.

Also, similar general purpose configuration data structure-pointing CSR mconfigptr (a part of the privileged architecture version 1.12) has an address of 0xf15.

If this CSR is going to be preserved, 0xf?? would be better than the current tentative address 0x3??.

Strictly speaking, xintstatus are also read-only but their addresses are okay to me (represents dynamic state information and updated by other CSR updates).

dansmathers commented 1 year ago

We are planning on moving these to parameters instead of CSRs. related to closed issue #80. The mclicbase register and clicinfo are likely to be replaced by the general discovery mechanism that is in development.

But we will leave this issue open until that is done. your point about addresses is taken. similar to #88 where intstatus are read-only but currently allocated in the r/w CSR range.

kasanovic commented 1 year ago

These should be reallocated to appropriate CSR ranges.

a4lg commented 1 year ago

Hmm, xintstatus also need to change (as pointed out in #88) considering CSRs containing dynamic state information like vl and vtype from V extension uses 0xC??, a URO CSR address range.

I confirmed PRs that remove mclicbase (#284) and move xintstatus CSRs to read-only CSR address space (#285).

kasanovic commented 1 year ago

Closed with https://github.com/riscv/riscv-fast-interrupt/pull/284 and https://github.com/riscv/riscv-fast-interrupt/pull/285