riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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move xintstatus to read-only CSR address range #285

Closed dansmathers closed 2 years ago

dansmathers commented 2 years ago

by convention, read-only CSRs have CSR address bits [11:10] = 11. for issue #88

Signed-off-by: Dan Smathers dan.smathers@seagate.com

kasanovic commented 2 years ago

All CSR numbers have to go through arch review for approval so might change.