search

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
Creative Commons Attribution 4.0 International
237 stars 49 forks source link

Single stepping an access to mnxti when dcsr.stepie==0 #291

Closed silabs-oysteink closed 1 year ago

silabs-oysteink commented 1 year ago

When single stepping with dcsr.stepie==0, interrupts are disabled and no interrupt should be taken while executing the stepped instruction.

What is the expected behavior of a CSR instruction accessing mnxti during a single step? Would it always behave as currently documented in the CLIC spec, or should it honor the dcsr.stepie bit and always return zero during a step if dcsr.stepie==0 ?

dansmathers commented 1 year ago

I would expect it would always behave as currently documented in the CLIC spec. It behaves as specified even if xstatus.xie is 0 so I think when dcsr.stepie is 0, it would be no different. Do you agree? We should discuss in the task group if additional clarification is required.

silabs-oysteink commented 1 year ago

Sounds good, I agree that with the behavior specified for xstatus.xie it should also not regard dcsr.stepie.

kasanovic commented 1 year ago

We discussed in TG meeting 1/17/2023. I agree with this rationale.

kasanovic commented 1 year ago

Closing as no change needed to CLIC spec.