riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
Creative Commons Attribution 4.0 International
237 stars 49 forks source link

Change addresses of mintstatus, sintstatus, uintstatus #294

Closed jhauser-us closed 1 year ago

jhauser-us commented 1 year ago

The current proposed addresses for CSRs mintstatus, sintstatus, and uintstatus place them in the middle of an unused region of read-only CSRs. See: https://docs.google.com/spreadsheets/d/1E6hXv76BH2mcMQUyT4h1qyIPf-rY76DixtnyvZ24umg/

Large regions of CSR addresses should be kept open for possible future arrays of CSRs (such as hpmcounter* and hpmcounter*h). To avoid them becoming an obstacle, it would be better for mintstatus, sintstatus, and uintstatus to be at locations 0xFB1, 0xDB1, and 0xCB1, respectively.

kasanovic commented 1 year ago

Closed with #300