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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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MNRET and mintthresh #319

Closed JamesKenneyImperas closed 1 year ago

JamesKenneyImperas commented 1 year ago

When Smrnmi is implemented, does MNRET also set mintthresh=0 when returning to non-M mode?

Thanks.

JamesKenneyImperas commented 1 year ago

closing, discovered this is documented.