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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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add CSRRW option for xnxti CSR #343

Closed dansmathers closed 1 year ago

dansmathers commented 1 year ago

for issue #308, allows setting mcause.mpil (used by xnxti to filter interrupts) as atomic with xnxti write.

kasanovic commented 1 year ago

The new form should not copy register source [4:0] into low bits of mstatus - we need to set the interrupt enable bit. Could use a csrrs instruction that checks level field in source register and always only sets the interrupt enable bit. This is slightly unusual csr instruction, but does not take any more encoding space as it was one of the previously unused forms of accessing the mnxti CSR.

dansmathers commented 1 year ago

closing. replaced by pull #344