Closed eroom1966 closed 1 year ago
I tried to comment on an issue already closed here https://github.com/riscv/riscv-fast-interrupt/issues/333#issuecomment-1708295950
I would like to repeat a question (asked previously) regarding the clearing of the inhv due to an xRET Previously @kasanovic said here
https://github.com/riscv/riscv-fast-interrupt/issues/154#issuecomment-839825594 Clearing inhv: "If the fetch is successful, the processor clears the low bit of the handler address, sets the PC to this handler address, then clears the xinhv bit in xcause."
This seems to have been removed from the specification by @dansmathers here https://github.com/riscv/riscv-fast-interrupt/pull/341 https://github.com/riscv/riscv-fast-interrupt/commit/d9ecea466ae5c7e16cd6e31b2ac432f682fd12f2
So my question reverts back to the original question posed https://github.com/riscv/riscv-fast-interrupt/issues/154#issuecomment-839507063 and answered in here to indicate that it is cleared https://github.com/riscv/riscv-fast-interrupt/issues/154#issuecomment-839825594
has the behavior changed ? if not and it is cleared, where do I find that in the updated specification - it is not obvious to me.
I tried to comment on an issue already closed here https://github.com/riscv/riscv-fast-interrupt/issues/333#issuecomment-1708295950
I would like to repeat a question (asked previously) regarding the clearing of the inhv due to an xRET Previously @kasanovic said here
https://github.com/riscv/riscv-fast-interrupt/issues/154#issuecomment-839825594 Clearing inhv: "If the fetch is successful, the processor clears the low bit of the handler address, sets the PC to this handler address, then clears the xinhv bit in xcause."
This seems to have been removed from the specification by @dansmathers here https://github.com/riscv/riscv-fast-interrupt/pull/341 https://github.com/riscv/riscv-fast-interrupt/commit/d9ecea466ae5c7e16cd6e31b2ac432f682fd12f2
So my question reverts back to the original question posed https://github.com/riscv/riscv-fast-interrupt/issues/154#issuecomment-839507063 and answered in here to indicate that it is cleared https://github.com/riscv/riscv-fast-interrupt/issues/154#issuecomment-839825594
has the behavior changed ? if not and it is cleared, where do I find that in the updated specification - it is not obvious to me.