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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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Behavior of interrupt pending bit for disabled interrupts #367

Closed tovine closed 9 months ago

tovine commented 10 months ago

Hi, I got a question about how the interrupt pending bit is supposed to behave if an interrupt is disabled (clicint[i].IE==0). For the level sensitive case it's simple, as the bit should just reflect the current state of the IRQ line, but for the edge triggered case there's no explicit description of what should happen in this case.

It's natural to assume that the interrupt pending bit could be independent of the interrupt enable bit when just reading the current text, but it would be nice with a small note in the spec to remove any uncertainty (even if that note just says "implementation defined").

tovine commented 9 months ago

Thanks for the clarification, Dan!