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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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xnxti with HW- and SW-vectored interrupts #381

Closed christian-herber-nxp closed 8 months ago

christian-herber-nxp commented 8 months ago

With the latest change around xnxti, I am not sure how things are still supposed to work. It is noted, that SHV and non-SHV ISRs might have a different SW interface, but this only discusses the differences in saved registers. There are more differences, which make things incompatible in my opinion

  1. vectored handles return with xret. xnxti initiated handlers have been jal-ed to and need to return with j, not an xret. Jumping with jal into a vectored handler and then return with an xret will crash your program.
  2. the trampolines go into the handlers with interrupts enabled. vectored handlers rely on interrupts being disabled when you jump into them

I can't see the argument behind checking xcause.xpil as working. This code would be in the critical path of a vectored interrupt handler, and thus not using xnxti would be faster. It could be sped up with a special instruction (or again a special CSR read), but for now, it really doesn't seem useful for SHV.

To avoid such unclarities, there should be an example on the handlers using xnxti including SHV and non-SHV handlers. Right now, I do not see this working when hardware vectoring is selective.

dansmathers commented 8 months ago

closed by #384. #370 merge taken out. #370 pull broke SW interrupt handler interface.