riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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clarify indirect CSR text for issue #377 #387

Closed dansmathers closed 8 months ago

dansmathers commented 8 months ago

Clarify that indirect CSR is needed for compliant implementations but the clicint registers can still be accessible via another method like memory-mapped access.