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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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Tentative assignment of base value of miselect/siselect for CLIC #391

Closed dansmathers closed 8 months ago

dansmathers commented 8 months ago

CLIC spec says this: The Indirect CSR Access allocated range for CLIC is TBD.

Sent the below email to tech-arch-review to ask for a tentative allocated range for CLIC.

CLIC has decided to use the Indirect CSR Access extension method (Smcsrind/Sscsrind) to access clicintctl/clicintattr/clicintip/clicintie/clicinttrig registers. CLIC can support up to 4096 interrupts so would need a range from 0x0 to 0x49F Can CLIC be given a tentative assignment of a base miselect/siselect value for this range?

dansmathers commented 8 months ago

From [RISC-V] [tech-chairs] ARC meeting minutes 2024/3/12: The [CLIC] spec was received and AR has begun reviewing the specifications. ARC allocated indirect CSR numbers 0x1000-0x14A0 for the new CSRs, which keeps this large allocation outside of the lower 12b space.

dansmathers commented 8 months ago

closed by pull #393