mnxti pseudo code clarification when rs1 == x0

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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mnxti pseudo code clarification when rs1 == x0 #395

Open dansmathers opened 7 months ago

dansmathers commented 7 months ago

it is confusing when doing csrr (rs1 == x0) whether clic.level should be compared against mcause.mpil or whether it should be compared to 0 (rs1[23:16]). I think the intent is that csr reads are compared to mcause.mpil.