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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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Make shv a per level property #400

Open christian-herber-nxp opened 2 months ago

christian-herber-nxp commented 2 months ago

This is a proposal to make the following change:

Currently, each interrupt can configured to use the hardware vectoring or not. This does create some challenges, as HW-vectored interrupts do not mix well with the nxti feature.

The change would make the shv bit a per level feature. This would reduce flip flops in implementation, and at the same time prevent HW vectored interrupts from ending the trampoline of the SW-vectored interrupts.

Same behavior could be achieved with the current definition through configuration, but then implementations would be wasting gates.

tovine commented 2 months ago

This seems reasonable. Out of curiousity: what were the original reasons to introduce selective hardware vectoring, and how would these be impacted by this change? My guess would be something like having the ability to use hardware vectoring for time critical interrupts, while having a simpler interrupt scheme for lower priority interrupts such as OS scheduling functions. And for this use case it shouldn't be a big problem - worst case you might have to add another level bit.