riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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xscratchcswl privilege behaviour not fully specified #406

Open Timmmm opened 2 months ago

Timmmm commented 2 months ago

When you write to Xscratchcswl you check (Ypil == zeros()) != (Yil == zeros()), but does Y = X or does Y = cur_privilege?

Unfortunately the example pseudocode is for accessing mscratchcswl where X and Y must both be machine mode. That isn't true when accessing sscratchcswl from machine mode though.

jb-brelot-nxp commented 1 month ago

related to issue #409

Need to clarify

jb-brelot-nxp commented 1 month ago

Verify that it has been fixed