issue #411 - Clarify that smclicshv ignores 1 or 2 LSBs of vector table entry (depending on IALIGN)

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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issue #411 - Clarify that smclicshv ignores 1 or 2 LSBs of vector table entry (depending on IALIGN) #417

Closed james-ball-qualcomm closed 1 month ago

james-ball-qualcomm commented 1 month ago

Note that the CLIC spec in all but one location was assuming masking for only the IALIGN=16 case. In that one location, it said: Note, next_pc is passed to fetch unit which will ignore 1 or 2 LSBs depending to IALIGN, so the masking is not shown above..

So, the CLIC spec already assumed the masking/ignoring of 1 or 2 LSBs is a function of IALIGN so with this PR, it now says that consistently and more clearly.

christian-herber-nxp commented 1 month ago

One suggestion still around mask: Let's rename to VTMASK, then this is consistent with VTBASE and a little bit more self-explaining

james-ball-qualcomm commented 1 month ago

Will rename MASK to VTMASK as requested.

christian-herber-nxp commented 1 month ago

lgtm. Make sure to squash and merge once done to avoid having all the commits on master.