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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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Recommend moving definition of indirect CSRs into their own chapter and clarifying they are accessed via M-mode or S-mode CSRs. #420

Open james-ball-qualcomm opened 5 days ago

james-ball-qualcomm commented 5 days ago

'The CLIC registers accessed via the indirect CSR mechanism don't belong to a particular mode (M or S). Instead, they exist outside the scope of any particular mode but are accessed via different indirect CSR addresses for M-mode or S-mode. The only difference is that M-mode access sees all the information in the indirect access CSRs where as S-mode "any interrupt i that is not accessible to S-mode appears as hard-wired zeros in clicintip[i], clicintie[i], clicintattr[i], and clicintctl[i]."

We should move the definition of these indirect access CSRs back into their own chapter and then just have smclic and ssclic chapters talk about how to access them from their respective modes and how S-mode sees a subset of the info (the quoted text in the previous chapter)?

james-ball-qualcomm commented 2 days ago

Do you all want me to make this change to the CLIC doc?

christian-herber-nxp commented 2 days ago

I think it is reasonable given the current organization. However, your suggestion made me realize that clicintattr.mode probably should not have the same behavior. This is a separate issue and i will open that for discussion. From my point of view, you can go ahead with this one.