Spec doesn't say to clear the second lowest bit of trap handler addresses

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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Open Timmmm opened 1 month ago

Timmmm commented 1 month ago

When setting PC to a vectored address on trap or xRET, the spec says:

If the fetch is successful, the hart clears the low bit of the handler address and sets the PC to this handler address.

This is presumably a mistake - it should clear the lowest bit if 16-bit instructions are supported, otherwise clear the lowest two bits.