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RISC-V Instruction Set Manual
https://riscv.org/
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Is it possible that x5 is misused by non-procedure call or return Scenario？ #1265

Open freemonkey91 opened 8 months ago

freemonkey91 commented 8 months ago

In unpriv spec：“A JAL instruction should push the return address onto a return-address stack (RAS) only when rd is x1 or x5” Based on my observations, in practical applications, subroutine calls and returns consistently use the x1 as recommanded, while x5(as alternate link register) is always paired with x1 specifically for coroutine-related functionalities. The question arises whether there are scenarios where x5 is independently used as a dedicated register for subroutine calls and returns, and if there is a possibility of incorrect usage where x5 might be mistakenly allocated as a regular register in inappropriate scenarios.

aswaterman commented 8 months ago

In the context of the base ISA, the RAS discipline is purely a microarchitectural hint. Beyond performance implications, x1 and x5 don’t have special properties.

Even when performance is a concern, microarchitectures should tolerate the use of x1 and x5 as temporary registers without an adverse perf impact. There’s nothing “mistaken” about using these registers for purposes other than return addresses.