search

riscv / riscv-isa-manual

RISC-V Instruction Set Manual
https://riscv.org/
Creative Commons Attribution 4.0 International
3.62k stars 629 forks source link

Difference between Ecall from user,supervisor,machine and Interrupts from machiine,supervisor in mcause encoding #1346

Open Omarezz123 opened 5 months ago

Omarezz123 commented 5 months ago

Why that difference is done in mcause that make only Interrupts , Ecall to have different mcause encoding according to privilege level (is that will affect the concept of delegation )while other exceptions like illegal instruction aren't not differ the privilege level they are taking in in their mcause encoding , also to have different Interrupts,Ecall privilege levels will accept the concept of all traps by default are taken in m-mode unless they are delegated (affect hardware design ? )(Are all traps will behave same ?) also to have Ecall instruction from s-mode means it comes when privilege level = s-mode ? >> that only check in hardware also to have timer Interrupts from s-mode means it comes when privilege level = s-mode ? >> that only check in hardware if so that means this concept is related to software design not hardware design ?

aswaterman commented 5 months ago

The delegation scheme is the explanation. Interrupts and exceptions are delegated based on their number. So, if we want to delegate selectively, we need different numbers.

For cases like illegal-instruction exceptions, we rationalize that they are uncommon enough that it’s acceptable to make the delegation decision in software, so that we don’t need additional cause codes in that case.

Omarezz123 commented 5 months ago

that means : Interrupt ,Ecall are Software delegated while other exceptions are Hardware delegated ?

and Interrupt is software delegated according to that : ? Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie are read-only zero

I have three questions if my explanation above is true : 1 .what means is maskable using the sie register (is that done in software not condition in hardware ?) 2what means .it becomes visible in the sip register (is that done in software not condition in hardware ?)

  1. why make software delegation and hardware delegation is more efficient As if considers Software delegation : hardware will go when interrupt , Ecall Comes only to M-mode and Software code then check in M-mode handler mcause register and according to it if it is For Ex : S/U-mode Ecall or S/U interupt and trap happens in S/U mode So can delegated and So transfer to s-mode So why that waste of instructions while if handled in hardware (Check delegation condition ) it will directly traps to delegated mode without pass through m-mode before going to desired trap
Omarezz123 commented 5 months ago

can a m-mode trap might be delegated if we are taking it in S mode especially i am asking for machine interrupt as i cant see why there is filed for Mahine interrupts in mideleg as spec says Traps never transition from a more-privileged mode to a less-privileged mode and also says that ecall from m-mode in medeleg is read only zero So why that concept is not applied for machine interrupts