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RISC-V Instruction Set Manual
https://riscv.org/
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Sstc description hasn't been merged well #1418

Open tariqkurd-repo opened 2 months ago

tariqkurd-repo commented 2 months ago

In this chapter:

Chapter 16. "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0.0

I don't think this text should be there anymore

To make it easy to understand the deltas from the current Priv 1.11/1.12 specs, this is written as the actual exact changes to be made to existing paragraphs of Priv spec text (or additional paragraphs within the existing text).

and in these chapters:

3.1.18. Machine Environment Configuration (menvcfg) Register 18.2.5. Hypervisor Environment Configuration Register (henvcfg)

there is this text:

The definition of the STCE field will be furnished by the forthcoming Sstc extension. Its allocation within [mh]envcfg may change prior to the....

Also the stce bit of Xenvcfg (which I was actually looking for when I found this) isn't mentioned in the Sstc chapter at all, so the definition of that field seems to be missing.

tariqkurd-repo commented 2 months ago

maybe it should be a different issue, but this is redundant too:

3.1.19. Machine Security Configuration (mseccfg) Register

redundant text:

The definitions of the RLB, MMWP, and MML fields will be furnished by the forthcoming PMP- enhancement extension, Smepmp. Their allocations within mseccfg may change prior to the ratification of that extension.

aswaterman commented 2 months ago

I believe @gfavor is aware that one of the many, many things on his to-do list is to better integrate the Sstc chapter. (Sstc is certainly not the only offender in this regard.)