As described by sepc:
RISC-V Privileged Architectures V20211203 8.1 Privilege Modes (p100)
VS-mode interrupts are globally disabled when executing in U-mode.
But in the spike:
When the executed privilege mode is less than hs, interrupts deleg to hs mode are enabled to trap. it seems that VS-mode interrupts will take trap to hs mode.
This confused me.
There are other questions of reading the spec:
1、What does Interrupts for lower-privilege modes mean? Interrupts deleg to lower-privilege modes or lower privileged mode interrupt (example: s mode software Interrupts < m mode software Interrupts)
2、What does VS-mode interrupts mean? Interrupts deleg to vs mode or VSS\VSE\VST Interrupts
As described by sepc: RISC-V Privileged Architectures V20211203 8.1 Privilege Modes (p100) VS-mode interrupts are globally disabled when executing in U-mode.
But in the spike: When the executed privilege mode is less than hs, interrupts deleg to hs mode are enabled to trap. it seems that VS-mode interrupts will take trap to hs mode.
This confused me.
There are other questions of reading the spec: 1、What does Interrupts for lower-privilege modes mean? Interrupts deleg to lower-privilege modes or lower privileged mode interrupt (example: s mode software Interrupts < m mode software Interrupts) 2、What does VS-mode interrupts mean? Interrupts deleg to vs mode or VSS\VSE\VST Interrupts