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RISC-V Instruction Set Manual
https://riscv.org/
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Whether the vs mode interrupt （VSS\VST\VSE） deleg to hs mode take trap to hs mode in u mode？ #1488

Open ZeyueShen opened 4 months ago

ZeyueShen commented 4 months ago

As described by sepc: image RISC-V Privileged Architectures V20211203 8.1 Privilege Modes （p100） VS-mode interrupts are globally disabled when executing in U-mode.

But in the spike： clipbord_1719907168745 When the executed privilege mode is less than hs, interrupts deleg to hs mode are enabled to trap. it seems that VS-mode interrupts will take trap to hs mode.

This confused me.

There are other questions of reading the spec: 1、What does Interrupts for lower-privilege modes mean？ Interrupts deleg to lower-privilege modes or lower privileged mode interrupt (example: s mode software Interrupts < m mode software Interrupts) image 2、What does VS-mode interrupts mean？ Interrupts deleg to vs mode or VSS\VSE\VST Interrupts image

zhaokunpengxa commented 3 months ago

can we consider?: vs-mode interrupt do not be delegated should be treated as hs-mode int?