riscv / riscv-isa-manual

RISC-V Instruction Set Manual
https://riscv.org/
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Accessing strong order memory space with vector instructions #1501

Open ZeyueShen opened 3 months ago

ZeyueShen commented 3 months ago

"Is it possible for vector instructions not to support accessing memory regions that have the 'strong order' address space attribute? If vector instructions do not support this, how should software respond when it attempts to access memory with such an attribute?"

gfavor commented 3 months ago

Yes. One way to approach this is to have PMA I/O regions not support vector memory accesses. Violations of a PMA region's supported attributes would, as always, result in an Access Fault on the offending instruction.

Note that you also have to worry about a vector instruction and its memory accesses straddling I/O and non-I/O regions - whether at the level of all of the instruction's accesses, or each individual memory access, or each individual element. Whatever your choices are, if you're taking an Access Fault in the middle of a vector instruction, then the standard precise exception and "vstart" semantics apply.