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RISC-V Instruction Set Manual
https://riscv.org/
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"RV32/64G instruction set listing" chapter should include _all_ the extensions #1517

Open enh-google opened 1 month ago

enh-google commented 1 month ago

the RV32/64G instruction set listing chapter is a really handy summary for those of us who have to work on assemblers/disassemblers/emulators. recent versions of the spec are a great improvement in terms of actually including the funct3 values [etc] in binary when introducing instructions (100 is more helpful than XOR as a funct3 "value", obviously). but the instruction set listing chapter is a great quick reference guide, and i don't understand why it's only G, not all the extensions described in the rest of the doc?

(obviously i'm at risk of having this resolved as "yeah, let's remove the whole chapter!" rather than "yeah, let's make that chapter complete!", but i would have to grudgingly admit that that's at least consistent :-) )

enh-google commented 1 month ago

(i'd assume there's educational value for students too.)

enh-google commented 1 month ago

actually, looking at the current latest (https://github.com/riscv/riscv-isa-manual/releases/tag/20240411) i see that Zfh is in the "G" chapter, so at least one extension author agreed with me :-)

enh-google commented 1 month ago

i'd also reference "26.8. RVC Instruction Set Listings" and ask why that's in a chapter of its own (and thus, if nothing else, harder to find) rather than combined with all the "G" instruction set listings? and why "C" gets this special treatment, but Zc* doesn't...

enh-google commented 1 month ago

recent versions of the spec are a great improvement in terms of actually including the funct3 values [etc] in binary when introducing instructions (100 is more helpful than XOR as a funct3 "value", obviously).

actually, i picked a bad example there :-)

although newer instructions (like for example "27.12.7 c.sext.b") are in this better format, old instructions haven't been retconned into the newer better format. specifically for xor, "2.4.2. Integer Register-Register Operations" currently still has "AND/OR/XOR" as the funct3 "value", forcing the reader to go and look at the "RV32/64G instruction set listing" chapter.