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riscv / riscv-isa-manual

RISC-V Instruction Set Manual
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software need for 16-byte atomic loads #1537

Open sorear opened 6 months ago

sorear commented 6 months ago

(Moved from riscv/riscv-profiles#144 per @kasanovic's request)

LLVM doesn't consider 16-byte CAS to be usable unless it comes with a primitive that can be used to implement atomic_load_16 on potentially read-only memory: https://github.com/llvm/llvm-project/pull/77814#issuecomment-1894198154

In that thread, there is speculation about adding a new zero-instruction extension that would give single-copy atomic behavior for a certain subset of vector loads and stores, in much the same way that Ziccif gives limited atomic behavior for a certain subset of instruction fetches. I believe that, if a zero-instruction extension were the preferred approach, it would not be inappropriate to define it here, at least for RV64.

Comments in riscv/riscv-profiles#144 appear to argue that the Ziccif analogy is incorrect and a separately ratified extension must be developed for double-width atomics. If that approach is taken and the ratification timeline for the new extension does not precede that of RVA23, is there any purpose in ratifying RVA23 with an option that LLVM considers incomplete and unusable?

kasanovic commented 2 months ago

Wider atomic loads will be considered as part of a broader 128b atomic support in a future extension, but will not be ready in time for RVA23. This future extension will be discussed on unprivileged mailing list initially, so closing this issue now for RVA23 profile. This repo will be merged into main ISA document after RVA23/RVB23 ratification, so moving issue there.