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RISC-V Instruction Set Manual
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C.S{LL,RL,RA}I64 are never actually defined in prose #1542

Open nwf-msr opened 1 month ago

nwf-msr commented 1 month ago

Looking at 982eac425ed3b36f087fce03ae8e0907fa575da7, at a glance, the only occurrences of the string "SRAI64" in the specification document are in table 40 of §28.7 and figure 4 of §28.8. Reading across the lines, as it were, one can conclude that C.SRAI64 is meant to be a reference back to §28.5.2 ("For RV128C, a shift amount of zero is used to encode a shift of 64.") but this isn't made explicit, and the use of a RV128C-specific mnemonic to refer to bit patterns even in RV{32,64}C is at least a little confusing.

Prior to having this understanding, I thought that table 28 in §28.7 failed to mention the C.SRAI shamt=0 hints defined in §28.5.2 ("For RV32C and RV64C, the shift amount must be non-zero; the code points with shamt=0 are HINTs."), but these are exactly the C.SRAI64 encodings that are enumerated.

Similar observations hold for C.SLLI64 and C.SRLI64.

aswaterman commented 1 month ago

These are RV128 instructions. RV128's definition is incomplete and probably should be removed from the spec, with the exception of the placeholder chapter describing the rough intent. If that were to happen, C.SLLI64 et al. would be removed at that time.