Which exception should be raised when directly accessing vstimecmp from VS and VU mode?

[zengderui]

Hi,

The Sstc extention says: "When this extension is implemented and STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an illegal instruction exception, "

The H-extension says: "When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception."

I'm wondering which exception should be raised when directly accessing vstimecmp when V=1?

[gfavor]

The current Priv spec says:

When this extension is implemented and STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an illegal instruction exception, STCE in henvcfg is readonly zero, and STIP in mip and sip reverts to its defined behavior as if this extension is not implemented. Further, if the H extension is implemented, then hip.VSTIP also reverts its defined behavior as if this extension is not implemented.

But when STCE in menvcfg is one and STCE in henvcfg is zero, an attempt to access stimecmp (really vstimecmp) when V = 1 raises a virtual instruction exception, and VSTIP in hip reverts to its defined behavior as if this extension is not implemented.

[zengderui]

Hi @gfavor , thanks for the quick response!

Can I interpret it this way?

when menvcfg.STCE is 0, stimecmp is disabled (considered unimplemented or non-existent) when henvcfg.STCE is 0, vstimecmp is disabled. Accesing a disabled/unimplemented/non-existent CSR always raises illegal instruction exception

Thereforce, when this extension is implemented and STCE in menvcfg is zero, accessing vstimecmp from VS/VS modes raises illegal instruction.

The accurate expression of H-extension should be: "When V=1, an attempt to read or write an enabled VS CSR directly by its own separate CSR address causes a virtual-instruction exception."

[gfavor]

Yes to when menvcfg.STCE=0. But the second paragraph says that when menvcfg.STCE=1 AND henvcfg.STCE=0, then vstimecmp is disabled.

The Priv spec does not require that unimplemented are trapped with an Illegal Instriction exception. They simply have a default definition of Reserved - which allows a fair amount of implementation freedom.

I'm not sure what your "The accurate expression of H-extension should be ..." statement is trying to point out that isn't clearly defined by the ISA specs?

The spec says that a vstimecmp access raises an illegal instruction exception irrespective of mode (other than M-mode) if menvcfg.STCE=0, and raises a virtual instruction exception when menvcfg.STCE=1 and henvcfg.STCE=0 and V=1. Conversely, when V=1 and menvcfg.STCE=1 and henvcfg.STCE=1 and hence stimecmp is accessible, then there should not be an exception.

As an orthogonal and general matter, the H extension says: When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception. (Attempts from U-mode cause an illegal-instruction exception as usual.)

[zengderui]

I don't understand why you say the statement of H-extension is "orthogonal". It appears to me the statements of Sstc-extension and H-extension are conflicting, in other words, Sstc does not strictly follow H.

For accessing vstimecmp directly from VS-mode or VU-mode (i.e. V = 1) when both H-extension and Sstc-extension are implemented, H-extension requires to raise virtual exception, but Sstc-extension says an illegal instruction exception will be raised if menvcfg.STCE is zero.

Is it allowed that some CSRs don't need to follow the statement of H-extension? i.e "When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception."

If it is allowed, maybe the statement can be changed to "Unless otherwise specified, when V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception."

[gfavor]

Menvcfg.STCE takes priority over what the H extension says. This is clear because when menvcfg.STCE=0, Sstc must appear to not be implemented. At which point the H extension saying that "accessing vstimecmp when V=1 and Sstc is implemented raises an exception" (irrespective of the exception type) is not applicable - since Sstc is not implemented.

[ved-rivos]

The H extension talks about the CSRs instroduced by the H extension and what it states is right.

The H extension also provides a more general HS-qualified rule. The HS-qualified rule states that an instruction, such as one that accesses a CSR, will cause a virtual-instruction exception instead of an illegal instruction exception if the attempted instruction is HS-qualified, i.e. valid to execute in HS-mode, but the instruction is prevented from executing at V=1 due to insufficient privilege or being disabled by a hypervisor CSR such as henvcfg or hcounteren.

The instruction to access vstimecmp would not be HS-qualfied if menvcfg.STCE was 0 since HS-mode itself cannot access it. When it is HS-qualified, i.e. menvcfg.STCE is 1, an access to vstimecmp from V=1 would still not be allowed since vstimecmp requires HS-mode privilege. However, now since the instruction is HS-qualified it will cause a virtual-instruction exception instead of an illegal instruction exception.

[zengderui]

Thanks for clarifying!