Weird behavior on dual core target

[yf13]

Dear experts,

I am debugging a multi-core M-mode rv32gc program in QEMU v6.2 RiscV virt target of dual SMP cores. Below is my function uint smp_protect(void) to help serialize access to a critical section from multi-cores:

/*
uint32_t smp_protect(void)
{ */
80000e68:   csrrci  a0,mstatus,8          // Disable IRQ, save in a0
80000e6c:   csrr    t1,mhartid
80000e70:   auipc   t0,0x88
80000e74:   addi    t0,t0,832 # 800891b0
80000e78:   lw      t2,4(t0)
80000e7c:   beq     t1,t2,80000e9e        // Skip locking if this is owner

80000e80:   lr.w    t2,(t0)               // LRSC lock loop
80000e84:   bnez    t2,80000e8e
80000e88:   li      t2,1
80000e8a:   sc.w    t2,t2,(t0)
80000e8e:   bnez    t2,80000e80           // Retry locking

80000e92:   fence   rw,rw
80000e96:   sw      t1,4(t0)              // Mark ownership
80000e9a:   fence

80000e9e:   lw      t1,8(t0)              // Increase lock count
80000ea2:   addi    t1,t1,1
80000ea4:   sw      t1,8(t0)
80000ea8:   ret                           // Return a0
/*
} */

However, I often got below weird situation where a0 at return holds an irrelevant value when running with GDB:

(gdb) i r mhartid priv mstatus a0 pc mie
mhartid        0x0  0
priv           0x3  prv:3 [Machine]
mstatus        0x80007880 SD:1 VM:00 MXR:0 PUM:0 MPRV:0 XS:0 FS:3 MPP:3 HPP:0 SPP:0 MPIE:1 HPIE:0 SPIE:0 UPIE:0 MIE:0 HIE:0 SIE:0 UIE:0
a0             0x6a 106
pc             0x80000ea8 0x80000ea8
mie            0x88 136

I am expecting a0 differs with mstatus only at the MIE bit, but it is not always true.

Any hints about what happened?

[aswaterman]

This is not a good forum for general RISC-V support. In this case, consider using the sw-dev mailing list. https://groups.google.com/a/groups.riscv.org/g/sw-dev