Can index-ordered and index-unordered VL*/VS* instructions be used to access device address space?

[Steven-Li-Xiaogang]

In most use cases, vector instructions are used to access memory space especially cacheable memory space, but seems there is no limitation to vector load/store instructions to access device address space which might be non-cacheable and non-bufferable or like ARM architecture with G,R,E features.

1. device address space we should use indexed-ordered load/store instruction if there is strictly access order requirement, also vstart should be set precise once there is trap in middle of this VL/VS operation?
2. if use non-index-ordered VL/VS operation, does it means an out of order IO access between uops in this instruction, access order can be different from one time to another.
3. was vstart with precise trap mandatory to be implemented in Vector 1.0 specification? if not, was it necessary to report vstart position while taking trap from an index-ordered instruction?

Thanks, StevenLee

[aswaterman]

1. Because an implementation might reorder element accesses for instructions other than indexed-ordered, you should only use indexed-ordered accesses for I/O where order matters. However, you might still use other vector loads and stores to I/O when order doesn't matter (e.g. accessing a RAM that is connected as I/O). Although precise vector traps allow relaxed handling of vstart for idempotent memory regions, the spec requires fully precise handling of vstart for non-idempotent memory regions.

2. Yes.

3. Zve* and V require precise vector traps.