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riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification
https://jira.riscv.org/browse/RVG-128
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Zjpm: Addresses reported in CSRs (stval, sepc) hold which addresses? #26

Closed deepak0414 closed 1 year ago

deepak0414 commented 1 year ago

Once PM is enabled, spec must define which values (pre-transformed address, address after masking out bits or ignore transformation address) go into CSRs (sepc, stval on PF) which report addresses to higher priv mode.

Future extensions (like MTE, etc) might fault on mismatches and depending on how fault definition is done, this information will be needed to resolve such faults.

martinmaas commented 1 year ago

Addressed in fd7220807e1405ba9b5de38d9d4ac26e73312128 (Section 2.6)

deepak0414 commented 1 year ago

as per commit it says

Values written to CSRs (e.g., stval) do not automatically have the ignore transformation applied before doing so. It is the responsibility of software to apply the ignore operation manually to such values before writing them into a CSR.

Issue is not about software writing values to CSR. It's about what should be the hart writing into let's say in stval when a page fault is encountered? Should it be the address after ignore transformation or before transformation?

Similarly what goes into epc when trap is delivered? address before transformation or after transformation (if masking on instruction fetch is enabled)

These need to be defined clearly for OS to have to right expectation.

martinmaas commented 1 year ago

The latest version of the spec (75e6aa4) now explicitly defines that hardware writes to a CSR store the transformed address (e.g., in the epc and stval cases listed above). On the other hand, software writes store the original address.