search

riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification
https://jira.riscv.org/browse/RVG-128
Creative Commons Attribution 4.0 International
159 stars 18 forks source link

Zjpm: nit - small note on IOMMU and memory accesses #27

Closed deepak0414 closed 11 months ago

deepak0414 commented 1 year ago

Although it is quite obvious that zjpm spec concerns only with CPU based accesses. Putting a note that device side accesses for shared virtual memory will be addressed by non-ISA spec will be useful.

Use cases like opencl [1] heavily use shared virtual memory between device side and cpu side.

[1] https://www.intel.com/content/www/us/en/developer/articles/technical/opencl-20-shared-virtual-memory-overview.html

martinmaas commented 1 year ago

Addressed in fd7220807e1405ba9b5de38d9d4ac26e73312128 (Section 2.6)

deepak0414 commented 1 year ago

Instead of saying this

Pointer masking only applies to accesses generated by instructions on the CPU (including CPU extensions such as an FPU). For example, it does not apply to accesses generated by the IOMMU or devices

It should be on the line

Zjpm specification concerns with pointer masking applied to memory accesses generated by instructions executing on the hart. Pointer masking on memory accesses from devices may be covered by non-ISA specifications like IOMMU specification

martinmaas commented 11 months ago

Quickly checking in about this item whether you still have this concern about the latest version of the spec. The suggestion from the architecture review committee was to remove this paragraph altogether since it is implied by the fact that pointer masking is an ISA extension.

deepak0414 commented 11 months ago

Yeah it was a nit anyways. That's fine by me if we close it.