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riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification
https://jira.riscv.org/browse/RVG-128
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Zjpm: Clarification on pointer masking when UXL = 1 or SXL = 1 (meaning 32bit) #35

Closed deepak0414 closed 9 months ago

deepak0414 commented 1 year ago

Spec is tied around with current translation mode and since 64bit architecture has spare bits, N is defined with respect to 64bit architecture.

Privileged spec allows setting of UXL = 1 in sstatus CSR. This pretty much makes U mode 32bit. As per spec, all instructions will ignore top 32bits in source operand and perform sign extension in destination.

Now hart can be in sv39 or sv48 or sv57 mode. All page table accesses will anyways be truncated to lower 4GB.

In this case I believe pointer masking is effectively disabled even if corresponding PM bit is enabled.

Can we add this clarification in the spec?

martinmaas commented 9 months ago

This is now addressed as of the latest version of the spec (*XL = 1 does not support pointer masking). Issue #41 has more context.