search

riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification
https://jira.riscv.org/browse/RVG-128
Creative Commons Attribution 4.0 International
162 stars 17 forks source link

SFENCE not required after enabling pointer masking #46

Closed ingallsj closed 11 months ago

ingallsj commented 1 year ago

regarding: https://github.com/riscv/riscv-j-extension/blob/ac6782d43813a8674a4704ff01ef00555dfe73d1/zjpm/instructions.adoc?plain=1#L36-L39

I agree that SFENCE should not be required after enabling/disabling pointer masking, because pointer masking applies to the effective address before translation.

Supporting comparison: the ARMv8 ARM does not include the allowance "This field is permitted to be cached in a TLB." in the description of the TCR_ELx.TBI/0/1 bits.

martinmaas commented 11 months ago

After discussing this in the group, this is now the official recommendation as per 92a88a2.