Pointer Masking Enable 2-bit CSR field: why?

riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification

https://jira.riscv.org/browse/RVG-128

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Pointer Masking Enable 2-bit CSR field: why? #47

Closed ingallsj closed 9 months ago

ingallsj commented 9 months ago

Why is this field two bits wide? What future use do we have in mind for the Reserved values 01/10? Is it for separate high/low controls, similar to ARM's TCR_ELx.TBI0/1?

https://github.com/riscv/riscv-j-extension/blob/ac6782d43813a8674a4704ff01ef00555dfe73d1/zjpm/instructions.adoc?plain=1#L10-L20

martinmaas commented 9 months ago

It is likely that we will want to support different values than N=16 in the future. Reserving the extra bit creates forward-compatibility for this anticipated scenario.

ingallsj commented 9 months ago

I'm guessing that future smaller values of the PME field will correspond to smaller values of N?

martinmaas commented 9 months ago

Either specific, smaller values of N, or we may use one value to indicate that N is dynamic/defined elsewhere/...