Update Pointer Masking proposal

riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification

https://jira.riscv.org/browse/RVG-128

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Closed Adam-pi3 closed 3 years ago

Adam-pi3 commented 3 years ago

Add XS bits for xMTE registers (for M, S and VS mode) which can be used as a discovery mechanism
Minor fixes