Question Regarding Pointer Masking Extension Implementation in RISC-V Sail

riscv / riscv-j-extension

Working Draft of the RISC-V J Extension Specification

https://jira.riscv.org/browse/RVG-128

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Closed HAMZA-AFZAL404 closed 5 months ago

HAMZA-AFZAL404 commented 5 months ago

Hi,

I just have few more questions regarding its implementation.

In machine mode or bare mode, what determines the number of masked bits? Are they dependent on the PMM bits in the mseccfg register?
If not, how is the number of masked bits determined in Bare mode?

Any guidance or references would be greatly appreciated. Thank you in advance for your time and assistance.

martinmaas commented 5 months ago

That's correct, the number of masked bits is determined by the PMM bits in the mseccfg register (i.e., 7 or 16).

martinmaas commented 5 months ago

(Closing this for now, please feel free to re-open if there are additional questions.)