riscv / riscv-opcodes

RISC-V Opcodes
https://riscv.org/
BSD 3-Clause "New" or "Revised" License
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Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH #239

Open dansmathers opened 8 months ago

dansmathers commented 8 months ago

update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs.

spec: https://github.com/riscv/riscv-fast-interrupt

Please see pull #226

dansmathers commented 8 months ago

pinging. Can this be reviewed? It holds up sail/arch tests/spike/gcc/llvm. Thanks