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riscv / riscv-opcodes

RISC-V Opcodes
https://riscv.org/
BSD 3-Clause "New" or "Revised" License
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The instructions vsll.vi, vsrl.vi and vsra.vi use zero-extended 5-bit immediate #95

Open XuJiandong opened 2 years ago

XuJiandong commented 2 years ago

According to: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#116-vector-single-width-shift-instructions

But in https://github.com/riscv/riscv-opcodes/blob/master/opcodes-rvv "simm5" is used. I think it should be "zimm5" instead.

aswaterman commented 2 years ago

It doesn't really matter; simm5 has no semantic meaning. It's just a token that means "bits 19..15".