destructive immediate bitfield insert

riscv / riscv-p-spec

RISC-V Packed SIMD Extension

https://jira.riscv.org/browse/RVG-129

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Open jnk0le opened 2 years ago

jnk0le commented 2 years ago

"place n bits from rs1 into [m+n-1 : m] of rd"

deprecates insb instruction
same thing as PULP p.insert
requires 2 5 bits of imm for RV32 and 2 6 for RV64
as P ext is already sourcing 3rd arg from rd (including INSB), it shouldn't be that big of a deal

jnk0le commented 2 years ago

Note that the eqivalent bfp from 0.94 bitmanip is a 3 instruction sequence, 1 of them being loop invariant in equivalent use case.

bitfield inserts are also usefull for uC register acces

// switch PLL (0b10) to HSE (0b01)
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | (RCC_CFGR_SW_HSE);

in this sample 0.94 bfp gives no advantage - andn + or + extra load of RCC_CFGR_SW_Msk solves it in 3 instructions