riscv / riscv-p-spec

RISC-V Packed SIMD Extension
https://jira.riscv.org/browse/RVG-129
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`CLROV` has fixed `rd` of `zero` #146

Open a4lg opened 2 years ago

a4lg commented 2 years ago

Because CLROV is an alias of CSRRCI x0, vxsat, 1, rd field is always zero (for x0 or zero).