RV32 vs. RV64 strategy for register-pair instructions

[aswaterman]

In the current design, some opcodes (e.g. KADD64) are defined to operate on 64 bits: i.e., a register pair in RV32, or a single register in RV64. This seems awkward to implement in configurable-XLEN processors: which/how many registers are accessed becomes a function of XLEN.

IMO, we should consider an alternate design that distinguishes the register-pair instructions and otherwise mimics the base ISA, e.g.:

• KADD operates on XLEN bits (similar to ADD in RV32/RV64)
• KADDW operates on 32 bits and sign-extends its result (RV64 only, similar to ADDW)
• KADD.PAIR (or some better name) operates on 2*XLEN bits (presumably RV32 only)

[marcfedorow]

I think that for the purposes of the P extension, the presence of KADD32 instruction (presumably RV64 only while KADD does the same thing on RV32) is necessary anyway. Thus IMO next line should be added to this suggestion:

• KADD32 operates on two packed 32-bit data blocks (RV64 only).

I am not sure if KADDW insn is necessary but it might be expected while SRAIW.u is presented in spec.