riscv / riscv-test-env

https://jira.riscv.org/browse/RVG-141
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Misaligned fetch bit must be excluded for RVC #12

Open as-sc opened 5 years ago

as-sc commented 5 years ago

https://github.com/riscv/riscv-test-env/blob/6f31769d091bbd2ef504308633fbe8a870641894/p/riscv_test.h#L160

pdonahue-ventana commented 4 years ago

18 fixes this so I think that this issue can be closed by someone with permission to do so.